The present invention relates to a data processor for parallelly executing plural instructions, and more particularly to a data processor suitable for executing plural instructions in a pipeline processing system (advanced control system).
In a data processor intended to speed up the processing by employing a system, e.g., a pipeline processing system, for processing plural instructions in parallel (including a system for processing instructions partially in an overlapped manner), if a preceding instruction writes an operation result in a register and a succeeding instruction uses the content of the same register to calculate an address, the succeeding instruction cannot start address calculation until the preceding instruction has written the operation result in the register, thus causing a delay in the processing. Such contention of data to be used in calculating an address is called "address conflict".
For the case where a preceding instruction is a so-called load instruction which writes a read-out operand in a register without subjecting it to arithmetic or logical operation and a succeeding instruction is in address conflict with the preceding instruction, a method of reducing a delay in the processing has been proposed in JP-A-56-46170 filed in the name of the present assignee.
If a preceding instruction writes an operation result in a register and a succeeding instruction reads an operand from the same register, the succeeding instruction cannot read the operand from the register until the preceding instruction has written the operation result in the register, thus causing a delay in the processing. Such operand contention on a register is called "register operand conflict" or simply "operand conflict".
According to a known conventional method of eliminating a delay in the processing to be caused by operand conflict, a short path for supplying an operation result of a preceding instruction to the input of an arithmetic or logical unit (ALU) is provided at an intermediate point of a write path of the ALU to a general purpose register, whereby the arithmetic or logical operation of a succeeding instruction which requires an operation result of the preceding instruction is performed without waiting for such a time when the operation result has been written in a designated general-purpose register. This method is called "a register operand wrap-around" or simply "operand wrap-around".
According to this method, if a preceding instruction is an instruction such as a LOAD instruction which requires no operation by an ALU, the operation of a succeeding instruction cannot start until the operation stage of the LOAD instruction has been completed.